As the feature size of semiconductor devices continue to shrink, the dimension of the transistor gate dielectric layer has been reduced to a critical limit. For example, in the 65 nm process, the thickness of the gate dielectric layer has been reduced to 1-2 nm. If the dimension of the gate dielectric layer is further reduced, leakage current and power consumption of the transistor will increase dramatically. For 32 nm and below technology nodes, a high-k dielectric layer and a gate metal layer are being utilized to reduce the leakage current and power consumption. A high-k dielectric layer may include HfO2, and a gate metal layer may include TiN.
However, a gate metal layer contains a large number of defects at grain boundaries, such as impurities, holes, etc. There are also defects such as excess charge present at the interface between the high-k gate dielectric layer and the gate metal layer.
In current techniques, after formation of the gate metal structure, a high temperature annealing of the high-k dielectric layer is carried out to reduce defects in the high-k dielectric layer and improve the uniform distribution of the threshold voltage. However, a high temperature annealing process may likely result in the evaporation of the gate metal structure and cause damage to the high-k dielectric layer and the gate metal layer.